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SQGATE is an educational simulator. Results may vary from physical logic hardware.
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STEP MODE Paused — press Step to propagate one gate
Properties

Select a gate

⌇ Waveform Viewer
0 ticks
Gates0 Wires0 Sel XY Ready — select a component from the library and click canvas to place
🗑 Delete
⧉ Duplicate
↺ Reset State
⊞ Package as Subcircuit
Prompt
🧪 Automated Testbench

Enter test vectors. Format: IN#1=0, IN#2=1 -> OUT#3=1 (one per line)

⊞ Truth Table Generator
Truth Table
Boolean Expressions
K-Map (2-var)
⬇ Export Circuit
Preview
🖼
PNG Image
High-res raster image — great for reports and presentations
SVG Vector
Scalable vector — perfect for documentation and LaTeX
📄
Project JSON
Full project snapshot — share or restore later
⚑ Design Rule Check

Run DRC to check your circuit for errors.

⊙ Circuit Templates

Click a template to place it on the canvas. Existing circuit is preserved — templates are placed at a free area.

⊕ Custom Gate Step 1 of 2
⊞ Custom Gate Library
🌐 Community Hub & Asset Marketplace

Explore and import CPU architectures, components, and libraries published by the SQGATE community.

16-Bit RISC-V CPU
by @AliceEDA
Pong Game Logic
by @BobBuilder
📝 Integrated ASM Compiler

Write Assembly code using custom macros.
Syntax: #DEFINE name hex_value, LABEL:, DATA. Values can be hex (0xFF) or decimal (255).

Ready to compile.
⟨/⟩ Verilog RTL
Structural
Behavioral
Import .v
⌨ Keyboard Shortcuts & Controls
Canvas
Click sidebarSelect component to place Click canvasPlace component on grid Drag gateMove gate to new position ScrollZoom in / out Middle-dragPan canvas Drag canvasRubber-band multi-select
Editing
Ctrl + ZUndo last action Ctrl + YRedo Ctrl + SSave project Del / BkspDelete selected gates Shift + ClickMulti-select gates EscCancel / deselect all
Wiring
Click out-pinStart drawing wire Click in-pinConnect wire to input Click wireDelete wire Dbl-click wireAdd net label Dbl-click gateRename gate
Advanced
Click INPUTToggle 0 ↔ 1 Dbl-click CLKSet frequency in Properties Dbl-click ROMOpen Hex Editor ⊞ PackageSave selection as Custom IC
COMPONENT QUICK REF
SR: S=R=1 → INVALID · D-Latch: E=1 transparent
D/JK/T FF: trigger on CLK ↑ · MUX: S=0→A, S=1→B
Merger: N bits → 1 bus · Splitter: 1 bus → N bits
ROM: 256×8 · RAM: A,Din,WE,CLK→Dout · ALU: +−∧∨⊕≪≫¬
ℹ️ About SQGATE

Free online logic gate simulator — design, simulate, and export Verilog in your browser.

What is SQGATE?
SQGATE is a powerful, client-side digital logic circuit simulator designed explicitly for computer science and electrical engineering students. Whether you are learning the basics of Boolean algebra or designing a complex 16-bit RISC-V CPU, SQGATE provides a frictionless, zero-latency environment to test your architectures.

Why use SQGATE?
Unlike traditional legacy EDA tools that require heavy desktop installations, SQGATE runs entirely in your web browser. This means you can build logic circuits on your laptop, tablet, or even your smartphone. Our proprietary simulation engine resolves gate propagations in real-time, allowing you to instantly visualize state changes with glowing wires and interactive toggle switches.

Advanced Features for Students
We go far beyond basic AND, OR, and NOT gates. SQGATE includes advanced components like D-Flip Flops, multiplexers, and 7-segment displays. Furthermore, our platform is actively expanding to include a Truth Table Generator, a Karnaugh Map (K-Map) Solver, and an integrated Verilog Simulator. You will soon be able to directly export your visual circuits into clean, synthesizable Verilog HDL code, perfectly bridging the gap between schematic design and hardware description languages.

Privacy-First Architecture
We believe student data should remain private. All of your circuit designs and project files are saved locally in your browser's memory. We do not require a login, and we do not store your designs on our servers, ensuring absolute privacy for your intellectual property.